(a) Field of the Invention
The present invention relates to an apparatus and method for driving a plasma display panel (PDP).
(b) Description of the Related Art
Recently, a PDP is being highlighted as a flat panel display in that it is advantageous over the other flat panel displays in regard to its high luminance, high luminous efficiency and wide viewing angle.
The PDP is a flat panel display that uses plasma generated by gas discharge to display characters or images. According to its size, the PDP can include tens to millions of pixels arranged in the form of a matrix. The structure of the PDP will now be described with reference to FIGS. 1 and 2.
FIG. 1 is a partial perspective view of a conventional PDP, and FIG. 2 shows an arrangement of electrodes in the conventional PDP.
As shown in FIG. 1, the conventional PDP includes two glass substrates 1 and 6 spaced apart from each other to face each other. Scan electrodes 4 and sustain electrodes 5 are formed in pairs in parallel on the glass substrate and are covered with a dielectric layer 2 and a protection film 3. Formed on the glass substrate 6 are a plurality of address electrodes 8, which are covered with an insulation layer 7. Barrier ribs 9 are formed in parallel with the address electrodes 8 on the insulation layer 7 such that each of them is interposed between the adjacent address electrodes 8. Phosphors 10 are coated on the surface of the insulation layer 7 and on both sides of each of the barrier ribs 9. The glass substrates 1 and 6 are arranged to face each other while defining a discharge space 11 therebetween so that the address electrodes 8 are orthogonal to the scan electrodes 4 and sustain electrodes 5. In the discharge space 11, discharge cells 12 are respectively formed at intersections between the address electrodes 8 and the pairs of scan electrodes 4 and sustain electrodes 5.
As shown in FIG. 2, a PDP includes a representative discharge cell 12 as schematically indicated and the electrodes of the PDP are arranged in the form of an n×m matrix. That is, a plurality of address electrodes A1 to Am are arranged in a column direction, and a plurality of scan electrodes Y1 to Yn and a plurality of sustain electrodes X1 to Xn are arranged in pairs in a row direction.
In the PDP, generally, one frame is divided into a plurality of sub-fields that are combined to express a gray scale. Each of the sub-fields is generally composed of a reset period, an address period and a sustain period.
In the reset period, wall charges formed by a previous sustain discharge are erased. Also, wall charges are set up to stably perform a next address discharge. In the address period, cells that are turned on and cells that are not turned on are selected in the panel, and wall charges are accumulated on the turned-on cells (i.e., addressed cells). In the sustain period, a sustain discharge occurs to actually display an image on the addressed cells.
Here, the term “wall charges” refers to charges that are formed proximate to the electrodes on the wall (for example, dielectric layer) of the discharge cells and stored on the electrodes. The wall charges do not actually touch the electrodes themselves because the dielectric layer covers the electrodes. However, for simplicity of description, the charges will be described herein as being “formed on”, “stored on” and/or “accumulated on” the electrodes. Further, the term “wall voltage” refers to a potential difference that is generated on the wall of the discharge cells by the wall charges.
In order to improve efficiency of the PDP, it has recently been proposed to raise the ratio of xenon (Xe) in discharge gas to more than 10%. The higher the ratio of Xe becomes, the higher a discharge firing voltage becomes. As a result and shown in the driving waveforms of FIG. 3, a voltage to a Y electrode is lowered to a negative voltage VscL in a Y ramp falling period (that begins in the reset period), and a scan pulse to the Y electrode is also lowered to the negative voltage VscL in the address period.
FIG. 4 is a circuit diagram of a driving circuit that applies the driving waveforms of FIG. 3 to X and Y electrodes.
As shown in FIG. 4, the driving circuit that applies the driving waveforms as shown in FIG. 3 includes a switch Ypp formed on a main path for causing a rising reset voltage to have no effect on a sustain discharge circuit, and a switch Ypn formed on the main path for causing a falling reset voltage to have no effect on other circuits when it is reduced to a voltage VscL lower than a base level of a sustain discharge voltage.
When a voltage Vs is applied to the Y electrode before a falling reset pulse is applied in FIG. 3, the drain voltage of the switch Ypn becomes the same voltage Vs as that of the Y electrode. Thereafter, if the falling reset pulse is applied to the Y electrode as a switch Yfr is turned on under the condition that the switch Ypn is turned off, the source voltage of the switch Ypn falls to the voltage VscL under the condition that the drain voltage thereof is the voltage Vs.
As a result, a high voltage (Vs-VscL) is applied between the drain and source of the switch Ypn. In order to withstand this high voltage, it is necessary to use a switch with a high withstand voltage as the switch Ypn, resulting in an increase in manufacturing cost.